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| AN127 Application Note LXT970 TO CS8952 REPLACEMENT GUIDE By James Ayres Introduction This document in conjunction with the CS8952 data sheet will guide the designer in replacing the Level One LXT970 with Cirrus Logic's Crystal LAN CS8952. Since both chips have a standard MII interface, the majority of the work is simply in routing the same signals to the different pin out of the CS8952. The assumptions used throughout this note are: 1) The CS8952 will be used in full auto negotiation mode, advertising 10/100Mb and Full/Half duplex. 2) A minimum of software configuration is desired. 3) The MAC will use the change of port status interrupt (MDINT on the LXT970, MII_INT on the CS8952) to minimize polling. 4) Phy Address 1. LXT970 PIN # 1 2 Name CRS FDS/MDINT Routing CS8952 Equiv Name Routing PIN # 49 CRS/Phyaddr[2] to MAC, 10K pulldown 26 MII_IRQ to MAC, 4.7K pullup The following table illustrates the pin to pin mapping and any needed pull up or pull down resistors. Certain configuration pins have no one to one mapping. In this case the pins necessary to match the LXT970 configuration are listed with their needed pull up or pull down resistor value. Power and ground pins are not listed. The LXT970 specifies 55 ohm series resistors on the MII interface. The CS8952 uses 33 ohm series resistors. The magnetics requirements for the CS8952 and the LXT970 are the same; a 1:1 turns ratio for both transmit and receive. Changing magnetics should not be necessary. However, the designer should evaluate the magnetics for suitability in their specific design. Please see the CS8952 datasheet for crystal requirements. 3 4 TRSTE MF4 5 MF3 to MAC Used as MDINT, connected to Mac, implies bit 17.1 is set to MAC 14 MII ADDR[4] low (implies CFG1 Low, FDE don't care) MII ADDR[3] low (Scrambler enabled) RX_EN to MAC Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved) OCT `98 AN127REV1 1 AN127 LXT970 PIN # 6 7 8 MF2 Name Routing Equiv PIN # Name CS8952 Routing 10 11 12 13 14 15 16 17 18 20 21 23 25 27 28 29 30 33 34 38 39 40 41 42 44 45 46 47 48 49 50 2 MII ADDR[2]/ low (4B, nibble mode) MF1 MII ADDR[1] low (DTE mode) MF0 MII ADDR[0]/ 3.5V (autoneg enabled) Notes for MF pins MF[4:0] tied to 10/100 autneg, MII address 1, scrambler enabled, DTE mode, full duplex 10/100 advertised, equivalent settings are used for the CS8952 control pins TEST Low 24,25 TEST0, TEST1 low XO (crystal out) N/C 97 XTAL_25O N/C XI (crystal in) 25/2.5 MHz Clock input 96 XTAL_25I 25 MHz Clock input FDE (full duplex enable) N/C 57,58 AutoNeg Control N/C CFG0 low NONE (Configuration pin 0) MDDIS high NONE (MDIO DISABLE) (all presets permanent) RESET to MAC 15 RESET to MAC FIBOP (fiber out positive) N/C 5 TX_NRZ+ N/C FIBON (fiber out negative) N/C 6 TX_NRZN/C TREF tied to center tap of NONE output transformer TPOP transformer 80 TX+ transformer TPON transformer 81 TXtransformer RBIAS 22K 1% to ground 86 RES 4.99K 1% to ground FIBIP N/C 7 RX_NRZ+ N/C FIBIN N/C 6 RX_NRZN/C TPIP transformer 91 RX+ transformer TPIN transformer 92 RXtransformer CFG1 (configuration pin 1) low NONE PWRDN to MAC 64 PWRDN to MAC LEDS LED 67 SPEED_100 LED (high efficiency) LEDC LED 73 LED5 (collision) LED LEDL LED 71 LED3 (link OK) LED LEDT LED 69 LED1 (tx active) LED LEDR LED 70 LED2 (rx active) LED MDIO to MAC 27 MDIO to MAC MDC 2.5MHz Clock 28 MDC 2.5MHz Clock RXD4 to MAC 37 RX_ERR/RXD[4]/ to MAC, 10K pulldown PHY_ADDR[4] RXD3 to MAC 29 RXD[3]PHY_ADDR[3]/ to MAC, 10K pulldown PHY_ADDR[3] RXD2 to MAC 30 RXD[2] to MAC RXD1 to MAC 31 RXD[1]/ to MAC, 10K pulldown PHY_ADDR[1] RXD0 to MAC 32 RXD[0] to MAC AN127REV1 AN127 LXT970 PIN # 51 54 55 56 57 58 59 60 61 62 63 64 Name RX_DV RX_CLK RX_ERR TX_ERR TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 COL Routing to MAC to MAC to MAC to MAC to MAC to MAC to MAC to MAC to MAC to MAC to MAC to MAC CS8952 Equiv Name Routing PIN # 33 RXDV/MII_DRV to MAC 36 RX_CLK to MAC 37 RX_ERR/RXD[4]/ to MAC, 10K pulldown PHY_ADDR[4] 38 TX_ERR/TXD[4] to MAC 42 TX_CLK to MAC 43 TX_EN to MAC 44 TXD[0] to MAC 45 TXD[1] to MAC 46 TXD[2] to MAC 47 TXD[3] to MAC 38 TX_ERR/TXD[4] to MAC 48 COL/PHYADD[0] to MAC, 10K pullup AN127REV1 3 |
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